1. Field of the Invention
This invention relates to a circuit and method of directly evaluating the single event transient SET performance of logic circuits.
2. Discussion of the Related Art
A previous methodology for evaluating SET performance of a logic circuit requires that two chains of SR latches 100 and 200 be built as shown respectively in FIGS. 1(a) and 1(b). The SET characteristic of chain 100 in FIG. 1(a) is measured and referred to as “baseline SET”. This is accomplished by irradiating measurement chain 100 and determining when the OUT1 output terminal has flipped data states. The baseline SET describes the SET performance of the chains of Set/Reset latches (SR1, SR2, SR3, . . . ) and buffer cells (102, 104, 106, . . . ) in between each of the stages. Typically, the number of stages (N) is large (for example 4096) to allow SET measurements to be done in a relatively short amount of time. The SET performance of the chain 200 in FIG. 1(b) is measured and described as “cumulative SET” because it contains both the SET performance of the “Target” (208, 210 . . . ) made out of a number of core cells (inverters) and the “baseline SET”, which measures the performance of the SR latches SR1, SR2, SR3, . . . and buffer cells 202, 204, 206, . . . similar to those found in measurement chain 100. Again, the cumulative SET is determined by irradiating measurement chain 200 and determining when the OUT2 output terminal has flipped data states. As a result of these two measurements, two SET performance curves are produced, and a third curve deduced, as is shown in the graph of FIG. 2. In the existing implementation, the “intrinsic SET” performance of the target cell is obtained by subtracting the “baseline SET” from the “cumulative SET”. Precise measurement is difficult to perform due to the reduced accuracy of measuring both the “baseline SET” and the “cumulative SET” curves.
What is desired is a circuit and method for directly measuring the SET performance of a target logic circuit.